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Cypress Semiconductor /psoc63 /SAR /INTR_SET

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Interpret as INTR_SET

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (EOS_SET)EOS_SET 0 (OVERFLOW_SET)OVERFLOW_SET 0 (FW_COLLISION_SET)FW_COLLISION_SET 0 (DSI_COLLISION_SET)DSI_COLLISION_SET 0 (INJ_EOC_SET)INJ_EOC_SET 0 (INJ_SATURATE_SET)INJ_SATURATE_SET 0 (INJ_RANGE_SET)INJ_RANGE_SET 0 (INJ_COLLISION_SET)INJ_COLLISION_SET

Description

Interrupt set request register

Fields

EOS_SET

Write with ‘1’ to set corresponding bit in interrupt request register.
OVERFLOW_SET

Write with ‘1’ to set corresponding bit in interrupt request register.
FW_COLLISION_SET

Write with ‘1’ to set corresponding bit in interrupt request register.
DSI_COLLISION_SET

Write with ‘1’ to set corresponding bit in interrupt request register.
INJ_EOC_SET

Write with ‘1’ to set corresponding bit in interrupt request register.
INJ_SATURATE_SET

Write with ‘1’ to set corresponding bit in interrupt request register.
INJ_RANGE_SET

Write with ‘1’ to set corresponding bit in interrupt request register.
INJ_COLLISION_SET

Write with ‘1’ to set corresponding bit in interrupt request register.

Links

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Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data